Semiconductor integrated circuits are traditionally designed and fabricated by first preparing a schematic diagram for hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. With standard cell technologies, for example, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library.
Each cell corresponds to a logical function unit or module, which is implemented by one or more transistors that are optimized for the cell. The logical designer selects the cells according to the number of loads that are attached at the cell, as well as an estimated interconnection required for routing. The cells in the cell library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell layout characteristics. The cell layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell's transistors and cell routing data. The cell characteristics include a cell propagation delay and a model of the cell's logical function. The propagation delay is a function of the internal delay and the output loading (or “fan-out”) of the cell.
A series of computer-aided design tools generates a netlist from the schematic diagram or HDL specification for the selected cells and the interconnections between the cells. The netlist can be used by a floor planner or a placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. The design tools then determine the output loading of each cell as a function of the number of loads attached to each cell, the placement of each cell, and the routes of the interconnections.
Conventionally, computer-aided, integrated circuit design tools utilize proprietary cell libraries, which include cell information, such as cell layout, timing, and signal routing information. Often, the layout design flow involves more than one design tool. Each such design tool can come from a different company. In such instances, the cell layouts created and/or utilized by such design tools may contain layout descriptions in different file formats and at different stages (e.g. logic design stage, circuit design stage, layout design stage, and so on) within the design layout process. For example, timing information, clocks, clock frequency parameters, input/output pins, attachment pad parameters, and so on, are often stored in different places and in different formats within the cell libraries of different design applications. Conventionally, if a cell module is created in one design tool that is needed or is to be used in an integrated circuit layout pattern produced by a second design tool, a decision has to be made with respect to conversion. Typically, a winner is chosen from the various design tools and all cells or cell libraries and related information are converted to the format of the “winning” design tool. Alternatively, one or more of a series of design tools are adapted to communicate with one another, and cell definitions are translated for use in other tools of the layout process.
The various formats of the layout information inhibit interactive design and potentially cause problems for design tools with respect to maintaining data consistency during the design cycle. Moreover, different design tools provide inconsistent user interfaces, meaning that a designer must either be familiar with multiple design tool interfaces, or the different tools must be operated by different designers. In the latter case, the design flow is partitioned among different engineers, each of which focuses on local optimizations, which may inhibit overall design optimization. Finally, if multiple design tools are utilized, iterations of timing and/or design optimization may introduce significant delays in the design process.
There is an ongoing need for systems and methods for communicating integrated circuit layout information between unrelated systems.